There has been developed a fin-type MIS type field effect transistor (hereinafter, referred to as “MISFET”) having a protrusion consisting of a semiconductor layer in which a main channel region is formed in side surface of the protrusion. A fin-type MISFET is known to be advantageous in terms of size reduction as well as improvement in various properties such as improvement in cutoff properties or carrier mobility and reduction in short channel effect and punch-through.
FIG. 1 shows a semiconductor device containing an MISFET having a single structure comprising a single cuboid semiconductor layer. FIG. 1(a) is a plan view of this semiconductor device and FIG. 1(b) is a cross-sectional view taken on line A-A′ of FIG. 1(a). In the structure shown in FIG. 1, on a silicon substrate 5 and a buried oxide film 4 is formed a cuboid semiconductor layer 38, on which is formed a gate insulating film 7. Furthermore, a gate electrode 6 is formed, which strides over the semiconductor layer 38 and the gate insulating film 7. A contact hole 13 is formed in gate electrode 22 on a substrate. In the contact hole 13 is buried a plug, which is connected to an upper interconnection 14. In this cuboid semiconductor layer 38, source/drain regions are formed in both sides of the gate electrode 6 and a channel region is formed in a region under the gate insulating film 7 (the upper and the side surfaces of the cuboid semiconductor layer 38). A channel width corresponds to the total of a height “H” of the cuboid semiconductor layer 38 multiplied by 2 and its width “a”, and a gate length corresponds to a width “d” of the gate electrode 6.
Japanese Patent Laid-open No. 2002-118255 has disclosed a multiple-fin MISFET having a plurality of cuboid semiconductor layers. FIG. 2(a) is a plan view of the semiconductor device and FIG. 2(b) is a cross-sectional view taken on line A-A′ of FIG. 2(a) (FIG. 2 shows a device having three cuboid semiconductor layers). In this semiconductor device, a central semiconductor layer 29, a semiconductor layer 28 in one end and a semiconductor layer 26 in the opposite end to the semiconductor layer 28 are arranged in parallel and a gate electrode 6 is formed such that it strides over the center of these semiconductor layers. In the semiconductor layer 28 in one end, a contact is not formed in the source/drain regions, or if formed, is not used as a transistor for applying current to a channel region (FIG. 2 shows an example where a contact with the source/drain regions are not formed in the semiconductor layer 28).
A multiple-fin MISFET has been manufactured by the following process. FIGS. 3 and 4 show an example of this manufacturing process. FIGS. 3 and 4 are cross-sectional views in the width direction of a semiconductor layer (corresponding to the cross-sectional view taken on line A-A′ of FIG. 2). First, a bonding or SIMOX method is used to prepare an SOI substrate consisting of a silicon wafer substrate 5, a SiO2 oxide film 4 and monocrystalline silicon film 2. Next, a SiO2 film 17 is formed on the surface of the SOI substrate by thermal oxidation and then, impurity is ion-implanted to the monocrystalline silicon film 2 (FIG. 3(a)). Then, the SiO2 film 17 is etched off (FIG. 3(b)). Subsequently, to the whole surface of the monocrystalline silicon film 2 is applied a photoresist 9, which is patterned by photolithography to form a resist mask 9 in a given pattern (FIG. 3(c)). Next, using the resist mask 9 as an etching mask, the monocrystalline silicon film 2 is anisotropically dry-etched, and then the resist mask 9 is removed to form a substantially cuboid semiconductor layer 38 with a given height on the SiO2 film 4 (FIG. 3(d)).
Next, a thin gate insulating film 7 is formed on the surface of the substantially cuboid monocrystalline silicon semiconductor layer 38 by, for example, thermal oxidation method or radical oxidation method. Furthermore, on the SiO2 film 7 is formed a polysilicon film 19 by CVD method and the polysilicon film 19 is made conductive by impurity diffusion. Then, on the polysilicon film 19 is formed a resist film 9 and the resist film 9 is patterned in a given pattern by photolithography (FIG. 4(a)). Using the resist film 9 as a mask, the polysilicon film 19 is selectively etched to form a gate electrode 6 (FIG. 4(b)).
Then, after extension ion-implantation, CVD method is used to deposit, for example, a silicon oxide film. Furthermore, the deposited insulator is left on the side wall (not shown) of the gate electrode 6 by anisotropic etching. Thus, an insulating film is formed on each of the side surface of the substantially cuboid semiconductor layer 38 and the sidewall of the gate electrode 6.
Subsequently, using the gate electrode 6 and the like as a mask, the substantially cuboid semiconductor layer 38 is doped with impurity to form a source region and a drain region.
Then, on the structure is formed an interlayer insulating film 16 such as SiO2 by CVD method, and then the interlayer insulating film 16 is planarized by CMP method. Then, a contact hole 13 is formed by photolithography and etching. The contact hole 13 is formed on the source/drain regions and the gate electrode 6. Subsequently, within the contact hole 13 are formed a tungsten film, an aluminum film, a TiN/Ti film and/or a laminated film of these. Thus, a contact plug is formed within the contact hole 13 (FIG. 4(c)). Next, an interconnection layer 14 electrically connecting to the contact plug is formed. The interconnection layer 14 is made of a conductive material containing aluminum as a main component. Then, a passivation film (not shown) is formed over these structures (FIG. 4(d)).
Japanese Patent Laid-open No. 2003-229575 has disclosed a manufacturing process wherein after pre-forming a stripe pattern convex semiconductor region over the whole surface of a substrate, the convex semiconductor region is removed except for necessary area to prevent proximity effect to the semiconductor region in both ends and to improve uniformity of etching.